このウェブサイトは Cookie を使用しています。このサイトを使用すると、Cookie の使用に同意したことになります。詳細については、こちらをご覧くださいプライバシーポリシー.

画像は参考用です。製品仕様を参照してください。

W971GG6SB25I

Name: W971GG6SB25I
Rating: 4.5 (10 reviews)

DRAM Chip DDR2 SDRAM 1Gbit 64Mx16 1.8V 84-Pin WBGA

ブランド: WINBOND ELECTRONICS CORP

製造元部品 #: W971GG6SB25I

パッケージ/ケース: 84-WBGA (8x12.5)

RoHS ステータス:

在庫状況: 6414 個、新しいオリジナル

製品の種類: DRAM

Warranty: 1 Year Ovaga Warranty - Find Out More

価格設定

*すべての価格は米ドルです

In Stock:6414 PCS

- +

簡単な見積もり

RFQを提出してください W971GG6SB25I またはメールでご連絡ください: Eメール: [email protected], 12時間以内にご連絡させていただきます。

量^*

Eメール^*

連絡先^*

会社

述べる

SDRAM - DDR2 Memory IC 1Gbit Parallel 200 MHz 57.5 ns 84-WBGA (8x12.5)

Power Supply: VDD, VDDQ = 1.8 V ± 0.1 V
Double Data Rate architecture: two data transfers per clock cycle
CAS Latency: 3, 4, 5, 6 and 7
Burst Length: 4 and 8
Bi-directional, differential data strobes (DQS and DQS ) are transmitted / received with data
Edge-aligned with Read data and center-aligned with Write data
DLL aligns DQ and DQS transitions with clock
Differential clock inputs (CLK and CLK )
Data masks (DM) for write data
Commands entered on each positive CLK edge, data and data mask are referenced to
both edges of DQS
Posted CAS programmable additive latency supported to make command and
data bus efficiency
Read Latency = Additive Latency plus CAS Latency (RL = AL + CL)
Off-Chip-Driver impedance adjustment (OCD) and On-Die-Termination (ODT) for
better signal quality
Auto-precharge operation for read and write bursts
Auto Refresh and Self Refresh modes
Precharged Power Down and Active Power Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
Packaged in WBGA 84 Ball (8x12.5 mm2), using Lead free materials with RoHS compliant

パラメータ	価値	パラメータ	価値
Rohs Code	Yes	Part Life Cycle Code	Obsolete
Ihs Manufacturer	WINBOND ELECTRONICS CORP	Package Description	TFBGA,
Reach Compliance Code	compliant	ECCN Code	EAR99
HTS Code	8542.32.00.32	Samacsys Manufacturer	Winbond
Access Mode	MULTI BANK PAGE BURST	Access Time-Max	0.4 ns
Additional Feature	AUTO/SELF REFRESH	JESD-30 Code	R-PBGA-B84
Length	12.5 mm	Memory Density	1073741824 bit
Memory IC Type	DDR DRAM	Memory Width	16
Number of Functions	1	Number of Ports	1
Number of Terminals	84	Number of Words	67108864 words
Number of Words Code	64000000	Operating Mode	SYNCHRONOUS
Organization	64MX16	Package Body Material	PLASTIC/EPOXY
Package Code	TFBGA	Package Shape	RECTANGULAR
Package Style	GRID ARRAY, THIN PROFILE, FINE PITCH	Peak Reflow Temperature (Cel)	NOT SPECIFIED
Seated Height-Max	1.2 mm	Self Refresh	YES
Supply Voltage-Max (Vsup)	1.9 V	Supply Voltage-Min (Vsup)	1.7 V
Supply Voltage-Nom (Vsup)	1.8 V	Surface Mount	YES
Technology	CMOS	Terminal Form	BALL
Terminal Pitch	0.8 mm	Terminal Position	BOTTOM
Time@Peak Reflow Temperature-Max (s)	NOT SPECIFIED

処理時間：送料は地域や国によって異なります。