HD64570

HD64570 概要

OverviewThe HD64570 serial communications adaptor (SCA) converts parallel data to serial data for communication with other devices. Its two independent, full-duplex transceivers support both synchronous (bit-synchronous or byte-synchronous) and asynchronous communication. Extensive protocol functions are provided.The SCA chip provides FIFO transmit and receive buffers with 32 stages each and a four-channel direct memory access controller (DMAC) with chained-block transfer facilities, enabling high speed transfer of data between SCA and memory. A built-in bus arbiter and 16-bit bus interface support high-performance system designs.Features• Data transfer rate: 50 bits/s to 7.1 Mbits/s (f = 10 MHz),   50 bits/s to 12 Mbits/s (f = 16.7 MHz)   50 bits/s to 5.7 Mbits/s (f = 8 MHz)*• Protocol support   _ Asynchronous (ASYNC): 5 to 8 bits + parity   _ Byte synchronous (COP): bisync, X.21, DDCMP, etc.   _ Bit synchronous (BOP): frame relay, HDLC, SDLC, X.25 link level (LAPB), LAPD etc.• Highly efficient data transfer: two 32-byte FIFOs (transmit/receive) per channel• Error detection: parity (asynchronous)   CRC-16, CRC-CCITT (byte- and bit-synchronous)      ™SDLC is a trademark of International Business Machine.   Transmission codes: NRZ, NRZI, FM0, FM1, Manchester   Operating modes: normal operating mode (full-duplex), auto echo, local loop back   DMA transfer: on-chip DMAC with four channels and chained-block transfer capability   Address space: 16 Mbytes   Bus interface: connects to 64180-, 8086-, and 68000-system 8-/16-bit MPU buses   Timers: time-out detection, etc.   Power supply: 5 V ± 10% (−20 to 75°C) for 10-MHz chip,                  5 V ± 5% (0 to 70°C) for 16.7-MHz chip                  5 V ± 10% (−40 to 85°C) for 8-MHz chip*

特徴

• Data transfer rate: 50 bits/s to 7.1 Mbits/s (f = 10 MHz),
• 50 bits/s to 12 Mbits/s (f = 16.7 MHz)
• 50 bits/s to 5.7 Mbits/s (f = 8 MHz)
• Protocol support
• _ Asynchronous (ASYNC): 5 to 8 bits + parity
• _ Byte synchronous (COP): bisync, X.21, DDCMP, etc.
• _ Bit synchronous (BOP): frame relay, HDLC, SDLC, X.25 link level (LAPB), LAPD etc.
• Highly efficient data transfer: two 32-byte FIFOs (transmit/receive) per channel
• Error detection: parity (asynchronous)
• CRC-16, CRC-CCITT (byte- and bit-synchronous)
• ™SDLC is a trademark of International Business Machine.
• Transmission codes: NRZ, NRZI, FM0, FM1, Manchester
• Operating modes: normal operating mode (full-duplex), auto echo, local loop back
• DMA transfer: on-chip DMAC with four channels and chained-block transfer capability
• Address space: 16 Mbytes
• Bus interface: connects to 64180-, 8086-, and 68000-system 8-/16-bit MPU buses
• Timers: time-out detection, etc.
• Power supply: 5 V ± 10% (−20 to 75°C) for 10-MHz chip,
• 5 V ± 5% (0 to 70°C) for 16.7-MHz chip
• 5 V ± 10% (−40 to 85°C) for 8-MHz chip